Gate arrays are arrays of semiconductor circuit elements formed in the substrate of a semiconductor device according to several standard designs usually up to the point where electrical interconnects are fabricated. The electrical interconnects are applied according to a custom pattern to cause the resulting integrated circuit to perform a particular desired function. The electrical interconnects usually comprise two layers of metal (or sometimes metal silicide for the first layer) lines, with vias formed between the two layers to connect the two layers at selected locations.
The formation of the gate arrays in a semiconductor substrate as a standard on-the-shelf item greatly reduces the time required to produce a finished semicustom integrated circuit after it has been ordered by the customer. However, in current semicustom integrated circuit processing techniques, three custom masking steps remain to be performed after a custom integrated circuit is ordered. These three steps are to deposit and pattern the first layer of metal, to deposit a layer of insulation and pattern the vias (openings in the insulation above the first layer of metal), and to deposit and pattern a second layer of metal, thus completing the interconnections to form the integrated circuit. A final passivation layer is usually applied and patterned for protection from the elements.